Technical Projects
Metaheuristic Chip Placement
Automated VLSI placement tool for a full chip design flow in XH018, using metaheuristic optimization integrated with Cadence Genus/Innovus. Industrial project with STMicroelectronics.
SAR ADC 8-bit with LUT Correction
Full mixed-signal design of a 100 kS/s, 8-bit charge-redistribution SAR ADC in XH018, with Python-based performance analysis (DNL/INL, SNDR, ENOB) and digital LUT correction for improved linearity.
Integrated PWM for Audio
Full-custom CMOS PWM integrated circuit for audio in XH018, from transistor-level schematic through physical layout and post-layout verification with DRC/LVS sign-off.
Charge-Sensitive Amplifier
Transistor-level design of a charge-sensitive amplifier with NMOS cascode input and CR-RC² shaper, achieving ENC below 100 e-rms. Full PVT corner and Monte Carlo analysis.
MNIST Neural Network on FPGA
Dense neural network for MNIST digit classification in VHDL on FPGA, using fixed-point arithmetic for hardware efficiency and achieving 98% classification accuracy.
16-Point FFT Pipeline
Pipelined Radix-4 FFT in VHDL for FPGA, achieving a 4.4x improvement in maximum operating frequency (44 to 193 MHz) through structural pipelining.
MEMS Pressure Instrumentation
Analog instrumentation chain for a capacitive MEMS pressure sensor at ~68 kHz, with TIA and per-stage noise budget. Validated with LTSpice and experimental measurements.
ECG Front-End PCB
Signal acquisition PCB for biomedical ECG, built around a high-CMRR instrumentation amplifier with active analog filtering for noise rejection.