About Me

Engineering student completing a double degree between Pontificia Universidad Católica de Chile and CentraleSupélec, alongside a Master 2 in Integration, Circuits and Systems (ICS) at Université Paris-Saclay. Focused on analog and mixed-signal IC design, with a complementary background in digital systems and scientific computing.

On the hardware side, my project work covers the full IC design flow: from transistor-level schematic design and simulation in Cadence, through physical layout with DRC/LVS sign-off, to post-layout characterization. This includes a full mixed-signal SAR ADC with digital LUT correction, a charge-sensitive amplifier targeting sub-100 e-rms noise, and metaheuristic-based VLSI placement optimization across a complete chip design flow.

Beyond hardware, I build the tools to understand and automate it. I have developed data pipelines for large-scale dataset analysis, EDA flow automation, and scientific computing, including a tool that cut a 500k-row analysis from hours to under 10 seconds.

I thrive in interdisciplinary environments and am driven to apply this hardware-software skillset to complex, high-impact challenges, drawing on my research background in biomedical engineering at Pontificia Universidad Católica de Chile. I am currently completing my final-year internship (stage de fin d'études) at STMicroelectronics Crolles, in the Product Reliability Enablement team.